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The tradeoff is complexity. The microcode must be carefully arranged so that the instructions in delay slots are either useful setup for both paths, or at least harmless if the redirect fires. Not every case is as clean as RETF. When a PLA redirect interrupts an LCALL, the return address is already pushed onto the microcode call stack (yes, the 386 has a microcode call stack) -- the redirected code must account for this stale entry. When multiple protection tests overlap, or when a redirect fires during a delay slot of another jump, the control flow becomes hard to reason about. During the FPGA core implementation, protection delay slot interactions were consistently the most difficult bugs to track down.
Crucially, this distribution of border points is agnostic of routing speed profiles. It’s based only on whether a road is passable or not. This means the same set of clusters and border points can be used for all car routing profiles (default, shortest, fuel-efficient) and all bicycle profiles (default, prefer flat terrain, etc.). Only the travel time/cost values of the shortcuts between these points change based on the profile. This is a massive factor in keeping storage down – map data only increased by about 0.5% per profile to store this HH-Routing structure!